A DAC is part of a feedback loop in a delta sigma modulator. Any non-linearity in the DAC directly degrades the linearity of the delta sigma modulator at low and medium frequencies. Hence, there is a need for highly linear DACs when used in high performance sigma-delta modulators.
The performance of modern integrated circuits is often limited by power consumption considerations. Integrated circuits often use complementary metal-oxide semiconductor (CMOS) transistor technology such as n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistors. Typically, NMOS and PMOS integrated circuits have four terminals including a drain, a source, a gate, and a body. The body terminal, which is sometimes referred to as the well or bulk terminal, can be biased to improve transistor performance. For example, a positive bias voltage can be applied to the body of a PMOS transistor and a negative bias voltage can be applied to the body of an NMOS transistor to change the threshold voltage, and therefore the performance, of the respective transistors. A body bias voltage typically should be regulated in some way because an excessive bias voltage can cause current to leak through a P-well or an N-well of a body-biased transistor. A bias voltage can decrease or increase an effective threshold voltage of each transistor, and for increased effective threshold voltage, the bias voltage reduces its leakage current. Any reduction in the leakage current can also reduce power consumption.
A body bias voltage tends to be a small value as in a range of a few hundred millivolts. Larger body bias voltages can have a significant adverse impact on a performance of a device. A general convention is to tie to an NMOS body to ground or to a most negative supply and to tie a PMOS body to a VDD, typically the highest voltage available. Increasing the NMOS body bias from ground to anything higher would reduce the threshold voltage, and consequently would cause a slight increase in leakage but the leakage currents would be extremely small until the NMOS body bias is increased to a point where the diode between source and body turns on and that is the point when a leakage current becomes significant.
Generally, body bias voltages can be generated off chip. However, this approach consumes some of the limited number of input-output pins in the integrated circuit. Consequently, to achieve a better design, a body bias voltage can be provided by an on-chip source to make room for other components in a very limited chip area and available power budget.